Bit and byte order

The data on the SPI bus is clocked with most significant bit first. All multi-byte register data are sent in little-endian byte order.

Clock polarity

Data is valid in the low-to-high transition of SCK. This is also known as the clock being active high with valid data on the leading clock edge.

Maximum clock speed

The maximum clock speed supported by Vision Controller is 2MHz. Clock speeds above this limit may result in unexpected behavior.

Setup time

The SPI slave unit has a setup time of 4 μs after the high-to-low transition of the CS signal.