SPI Commands
The available SPI commands are listed in the table below.
| Command | Binary Value | Description |
| WRITE_REG | 01AAAAAA | Write register value, AAAAAA is 6 bit register addres |
| READ_REG | 00AAAAAA | Read register value, AAAAAA is 6 bit register addres |
| READ_DMX | 10000001 | Read most recent DMX frame. No tearing is allowed, so the frame must be double-buffered on Vision Controller chip. When DMX settings changed may not use actual frame and read more bytes. [Must be read if source is VISION PROTOCOL] |
| READ_RDM | 10000011 | Read most recent RDM frame. After all message bytes are transferred, any more bytes are considered invalid. Use Message Length field of RDM frame to determine packet size. [Must always be read] |
| READ_DFU | 10000111 | Read DFU Packet. Each Packet has a unique ID number. Length is variable up to 200Byte. Development app uses 128 Byte. packetNr is stored in Big Endian not Little Endian! |
| WRITE_DMX | 10010001 | Write DMX frame. Frame is complete when CS is going high [Only if source is not VISION PROTOCOL] |
| WRITE_RDM | 10010011 | Write RDM frame. Frame is complete when CS is going high |
| WRITE_DFU | 10010111 | Write DFU Response after Start, Packet, Stop |
| NOP | 11111111 | No-operation. |
WRITE_REG
This function is used to write to a specific register.
READ_REG
This function is used to read to a specific register.
READ_DMX
This function must be used to derive input values for VISION PROTOCOL as selected input source. The data stream is defined as the following:
| data[0] | data[1] | data[2] | data[2] | … | data[512] |
|---|---|---|---|---|---|
| iQ.dmxMode | dmx[1] | dmx[2] | dmx[3] | … | dmx[512] |
READ_RDM
Raw RDM byte stream. After all message bytes are transferred, any more bytes are considered invalid. Use Message Length field of RDM frame to determine packet size.
READ_DFU
Function for reading firmware packets.
| data[0] | data[1] | data[2] | data[2] | … | data[202] |
|---|---|---|---|---|---|
| packetNr | packetNr | data[0] | dmx[1] | … | dmx[200] |
Each Packet has a unique 16bit ID number. Length is variable up to 200Byte. Development app uses 128 Byte. packetNr is stored in Big Endian not Little Endian! (Legacy Mode)
WRITE_DMX
Used for writing the fixtures DMX input to this register. This can be used to diagnose the dmx input of the fixture or to transmit the dmx frame over Vision Protocol. Use a maximum refreshrate up to 20ms. [Only if source is not Vision Protocol]
SPI Register Map
| REGISTER MAP | |||||
| Address | Register Name | Bit | Type | Reset Value | Description |
| 0x02 | SYSTEM STATE | 0 – 8 | R/W | Trigger different System States. (SYSTEM STATE) | |
| 0x04 | CUSTOM COMMAND | 0 – var | W | Custom command | |
| Command | 0 – 7 | W | *internal | ||
| Data | var | W | – | *internal | |
| 0x05 | START_DFU_IQ_CONTROLLER | 0 – 7 | Trigger DFU mode of the iQ.Controller | ||
| Vision Controller goes into DFU Mode | 0 | W | – | Write 1 triggers Module DFU Mode | |
| 0x06 | STATUS | 0 – 7 | R/W | Status Flags | |
| IQ_LINKED | 0 | R/W | 0 | Fixture is linked to a certain network. 0 – not linked, 1 – linked. Write 1 to unlink from network. | |
| RF_LINK | 1 | R | – | Active Radio Transmission | |
| IQ_STATE | 8-15 | R | Detailed IQ.State (IQ_STATE) | ||
| 0x07 | IRQ_MASK | 0 – 6 | Interrupt Pin Mask | ||
| EN_RX_DMX_IRQ | 0 | R/W | 1 | Enable interrupt pin output when RX_DMX_IRQ goes high | |
| EN_RX_RDM_IRQ | 1 | R/W | 1 | Enable interrupt pin output when RX_RDM_IRQ goes high | |
| EN_NFC_WAKEUP | 2 | R/W | 1 | Enable interrupt pin output when NFC_WakeUp_IRQ goes high | |
| EN_RF_LINK_IRQ | 3 | R/W | 1 | Enable interrupt pin output when RF_LINK_IRQ goes high | |
| EN_DFU_START_IRQ | 4 | R/W | 1 | Enable interrupt pin output when DFU_START_IRQ goes high | |
| EN_DFU_PACKET_IRQ | 5 | R/W | 1 | Enable interrupt pin output when DFU_PACKET_IRQ goes high | |
| EN_DFU_STOP_IRQ | 6 | R/W | 1 | Enable interrupt pin output when DFU_STOP_IRQ goes high | |
| 0x08 | IRQ_FLAGS | 0 – 7 | R/W | 0 | Interrupt Flags |
| SYS_RESTARTED | 0 | R/W | 0 | System startup or restart from error/ dfu. Make sure to set config if used | |
| RX_DMX_IRQ | 1 | R/W | 0 | Different DMX frame received | |
| RX_RDM_IRQ | 2 | R/W | 0 | Complete RDM frame received | |
| NFC_WAKEUP | 3 | R/W | Wake Up through NFC | ||
| RF_LINK_IRQ | 4 | R/W | 0 | RF link status changed | |
| DFU_START_IRQ | 5 | R/W | 0 | DFU Update requested. DFU Response required. (Write DFU) | |
| DFU_PACKET_IRQ | 6 | R/W | 0 | DFU Packet received and must be read (Read DFU) ERROR: DFU Response | |
| DFU_STOP_IRQ | 7 | R/W | 0 | DFU Finished. DFU Response required. (Write DFU) | |
| 0x0A | RDM_ID | RDM ID of device | |||
| RDM ID | 0 – 47 | R/W | |||
| 0x0D | INFORMATION | ||||
| UUID | 0 -15 | R | 0 | Actual UUID (uint16_t) | |
| DEVICE_COUNT | 16 – 31 | R | 0 | Actual Fixture count (uint16_t) | |
| MODE | 32 – 39 | R | 0 | Actual Network Mode | |
| QUALITY | 40 – 47 | R | 0 | Actual Network Signal Quality 0 – 100: Quality in % | |
| CID | 48 – 55 | R | 0 | Actual Custom application ID | |
| NAME | 56 -151 | R | 0 | Actual Network Name (char[]) | |
| IDENTIFIER | 152-175 | R | 0 | Actual Network Identifier (uint8_t[]) | |
| 0x0E | IQ_CONTROLLER_VERSION | ||||
| FW_MAJOR | 0 – 7 | R | |||
| FW_MINOR | 8 – 15 | R | |||
| FW_PATCH | 16 – 23 | R | |||
| FW_RELEASE | 24 – 31 | R | |||
| BL_MAJOR | 32 – 39 | R | |||
| BL_MINOR | 40 – 47 | R | |||
| BL_PATCH | 48 – 55 | R | |||
| BL_RELEASE | 56 – 63 | R | |||
| HW_VERSION | 64 – 95 | R | Part Variant, Hardware version and Production configuration, encoded as ASCII | ||
| 0x0F | RTC | ||||
| UTC_VALUE | 0 – 63 | R/W | Read Write RTC Value in UTC Format | ||
| 0x10 | ACCELERATION_SENSOR | Only if motion sensor available | |||
| X_AXIS | 0 – 15 | R | signed short (Little Endian) | ||
| Y_AXIS | 16 – 31 | R | signed short (Little Endian) | ||
| Z_AXIS | 32 – 47 | R | signed short (Little Endian) | ||
| SENSOR_AVAILABLE | 48 – 55 | R | 0: not available , 1: available | ||
| 0x11 | IQ_CONTROLLER_CPUID | 0 – 63 | R | Unique CPU ID iQ.Controller | |
Definitions
Following definitions for the register are defined:
| Register | Value | Name | Description |
|---|---|---|---|
| SYSTEM STATE | |||
| 0 | SYS_STATE_INVALID | Not configured | |
| 2 | SYS_STATE_NORMAL | Normal Operation | |
| 3 | SYS_STATE_OPEN | Trigger Open Operation with Timeout | |
| 4 | SYS_STATE_PROTECTED | Interface disabled | |
| IQ_STATE | |||
| 0 | IQ_STATE_UNLINKED | Unlinked | |
| 1 | IQ_STATE_LINKED | linked | |
| 2 | IQ_STATE_ACTIVE | Linked and active | |
| 3 | IQ_STATE_MASTER | Linked and Master | |
| 4 | IQ_STATE_INACTIVE | Linked and Inactive |